Self-aligned low resistance buried contact process

ABSTRACT

A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral margin of the buried contact implanted through the exposed part of the thin layer of silicon lowers the threshold voltage of any parasitic MOS device which may be created between the buried contact and the remote N+source or drain structure.

FIELD OF THE INVENTION

This invention relates to semi-conductor integrated circuits, and morespecifically to the creation of reliable buried contacts between atransistor element and a remote diffusion area. The invention hasparticular applicability to the fabrication of integrated memorycircuits.

BACKGROUND OF THE INVENTION

Buried contacts are used in the fabrication of integrated circuits inorder to establish current pathways through the underlying substraterather than on the top surface of the circuit. Buried contacts ensureelectrical isolation from other parts of the circuit, and leave the topsurface free for use in establishing other connections and outsidecontacts giving access to the circuit.

For instance, in the fabrication of Static Random Access Memories(SRAMs), a buried contact is used to link the gate of one transistor tothe drain of another in a paired transistor memory cell, as explained inU.S. Pat. No. 5,064,776 Roberts.

In the fabrication of Dynamic Random Access Memories (DRAMs), a buriedcontact is used between a storage capacitor and the source or drain ofits controlling transistor.

Integrated circuit designers are forever trying to improve theconductive quality of buried contacts under the constraint ofever-increasing circuit complexity and demand for miniaturization.

A buried contact must retain a low resistive path minimal currentleakage to other parts of the circuit, and reduce the volume.

Buried contacts are typically created by diffusion or implantation ofions in the upper region of the circuit substrate through an opening inan insulating silicon oxide layer laid over the upper surface of thesubstrate.

The diffusion or implantation of the buried contact must extend beyondthe periphery of the window open near or under a gate or storagecapacitor structure in order to reach the source or drain region towhich the gate or capacitor must be connected. Insufficient diffusion orimplantation leaving too large a spacing between the edge of the buriedcontact and the outer edge of the polysilicon defining the source ordrain may result in the creation of a parasitic MOS device having arelatively high threshold voltage (Vt) between the buried contact andthe remote source or drain location. This parasitic MOS device mayincrease the buried contact resistance and degrade the circuitperformance. The diffusion of the buried contact into the substrate isusually controlled by the size of the window, the type and duration ofthe diffusion or implantation process, and the judicious selection ofdoping elements.

Various techniques based on successive diffusion or punch-throughimplantations which have been used in the past require multiple maskingsteps which increase the fabrication complexity, processing time andcost.

SUMMARY OF THE INVENTION

The principal and secondary objects of this invention are to provide areliable technique for diffusing buried contacts through a relativelysmall window while avoiding the formation of parasitic MOS devicesbetween the buried contact and the remote source or drain diffusionarea; and to do so with a limited number of masking steps.

These and other objects are achieved by the buried contact by thecreation of phosphorous or arsenic implantation through a relativelynarrow window cut in the insulating silicon oxide layer and a thin layerof silicon laid over it. The edge of the photoresist used to etch thewindow are descumed back a small amount in order to allow implantationof a marginal zone through the exposed section of the silicon layer.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a cross-sectional view of the initial layer depositionprocess;

FIG. 2 is a cross-sectional view of the buried contact window etching;

FIG. 3 is a cross-sectional view of the buried contact windowenlargement, and implantation processes; and

FIG. 4 is a cross-sectional view of the polysilicon layering; and

FIG. 5 is a cross-sectional view of the final buried contact structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

Referring now to the drawing, the invention will be described inconnection with the fabrication of a DRAM die.

FIG. 1 illustrates a section 11 of an integrated circuit including theend section 12 of a dogbone-shaped wafer formed by a lateral bulge inthe silicon oxide layer 13 grown over a P-doped substrate 14. The endsection 12 is to be used in forming a storage capacitor to be linked bya buried contact to a remote N+diffused area associated with the sourceor drain of a controlling transistor. A thin first layer 15 ofpolysilicon may first be deposited over the insulating oxide layer 13.The wafer is then covered with a photoresist 16. The photoresist isexposed through a mask, then developed to create a void 17 over the areawhere the buried contact is to be formed.

As shown in FIG. 2, the void is used to etch a window 18 through thethin polysilicon layer 15 and the oxide layer 13. The periphery of thevoid 17 in the photoresist 16 is descumed or cut back to expose aperipheral margin 19 of polysilicon around the window 18 as illustratedin FIG. 3. Phosphorous or arsenic is then implanted as indicated by thearrows 20 by a punch-through implant process or other appropriatetechnique creating a N+doped zone 21 that extends under the entiredescumed width of the photoresist.

As shown in FIG. 4, a second layer 22 of polysilicon is deposited thendoped and patterned to create the storage capacitor plate, and thesource, gate and drain of the transistor.

FIG. 5 illustrates the buried contact 23 after its diffusion and thediffusion 24 of the transistor source or drain area. It should be notedthat any parasitic MOS device which may have been created between theburied contact 23 and the source or drain zone 24 is bridged by theperipheral area 26 of the phosphorous or arsenic implant. This extensionof the implant greatly reduces the threshold voltage of the parasiticMOS device. Typically, a 0.2 micrometer etch back of the photoresistaround the buried contact opening will be adequate in order to create alow threshold MOS device zone bridging arsenic-doped diffusions of theburied contact and source/drain structure. The window enlargementprocess may be used without depositing the first layer 15 ofpolysilicon.

It should be noted that the above-described process can be used inconnection with other types of buried contacts such as those in use inconnecting the gate of one transistor to the drain of another in a SRAMcircuit.

While the preferred embodiments of the invention have been described,modifications can be made and other embodiments may be devised withoutdeparting from the spirit of the invention and the scope of the appendedclaims.

What is claimed is:
 1. A process for forming a buried contact between atransistor element at the surface of a substrate and a remote diffusionregion which comprises the steps of:growing an insulation layer ofsilicon oxide over said surface; depositing a first layer of polysiliconover said insulation layer; depositing a photoresist over said firstpolysilicon layer; patterning a window in said photoresist; etching saidfirst polysilicon layer and oxide layer through said window; descumingthe edges of said photoresist window to expose a peripheral width ofsaid first polysilicon layer; implanting a doping element into saidsubstrate through said descumed window and peripheral width to form acentral zone of buried contact aligned with said window and a peripheralzone of buried contact substantially aligned with said peripheral width,wherein said peripheral width receives a lesser amount of doping elementthan said central zone; removing said photoresist after said implanting;depositing a second layer of polysilicon over said first layer; andpatterning said second layer to form the source, drain and other partsof said transistor, and access to said buried contact.
 2. The process ofclaim 1, wherein the step of implanting comprises implanting into saidsubstrate a doping element selected from a group consisting of arsenicand phosphorous. .Iadd.
 3. A process for forming a buried contactbetween a transistor element at the surface of a substrate and a remotediffusion region which comprises the steps of:growing an insulationlayer of silicon oxide over said surface; depositing a first layer ofpolysilicon over said insulation layer; selectively forming an etchresist over said first polysilicon layer to define a window; etchingsaid first polysilicon layer and oxide layer exposed by said window;exposing a peripheral width of said first polysilicon layer adjacentsaid window; implanting a doping element into said substrate throughsaid window and peripheral width to form a central zone of buriedcontact aligned with said window and a peripheral zone of buried contactsubstantially aligned with said peripheral width, wherein saidperipheral zone receives a lesser amount of doping element than saidcentral zone; removing said etch resist after said implanting;depositing a second layer of polysilicon over said first layer; andpatterning said second layer to form the source, drain and other partsof said transistor, and access to said buried contact..Iaddend..Iadd.4.The process of claim 3, wherein the step of implanting comprisesimplanting into said substrate a doping element selected from a groupconsisting of arsenic and phosphorous..Iaddend..Iadd.5. A process forforming a buried contact between a transistor element at the surface ofa substrate and a remote diffusion region which comprises the stepsof:growing an insulation layer of silicon oxide over said surface;depositing a first layer of polysilicon over said insulation layer;selectively forming a resist over said first polysilicon layer to definea window; removing said first polysilicon layer and oxide layer exposedby said window; exposing a peripheral width of said first polysiliconlayer adjacent said window; implanting a doping element into saidsubstrate through said window and peripheral width to form a centralzone of buried contact aligned with said window and a peripheral zone ofburied contact substantially aligned with said peripheral width, whereinsaid peripheral zone receives a lesser amount of doping element thansaid central zone; removing said resist after said implanting; forming aselectively patterned second layer of polysilicon over said first layerto form source, drain and other parts of said transistor, and access tosaid buried contact..Iaddend..Iadd.6. The process of claim 5, whereinthe step of implanting comprises implanting into said substrate a dopingelement selected from a group consisting of arsenic andphosphorous..Iaddend..Iadd.7. A process for forming a buried contactbetween a transistor element at the surface of a substrate and a remotediffusion region which comprises the steps of:forming an insulationlayer over said surface; depositing a polysilicon layer over saidinsulation layer; selectively defining a window on said polysiliconlayer; removing said polysilicon layer and underlying insulation layerexposed by said window; defining a peripheral width of said polysiliconlayer adjacent said window; implanting a doping element into saidsubstrate through said window and peripheral width to form a centralzone of buried contact aligned with said window and a peripheral zone ofburied contact substantially aligned with said peripheral width, whereinsaid peripheral zone receives a lesser amount of doping element thansaid central zone; and forming a selectively patterned conductive layerover said polysilicon layer to form source, drain and other parts ofsaid transistor, and access to said buried contact..Iaddend..Iadd.8. Theprocess of claim 7, wherein the step of implanting comprises implantinginto said substrate a doping element selected from a group consisting ofarsenic and phosphorous..Iaddend..Iadd.9. A process for forming a buriedcontact between a transistor element at the surface of a substrate and aremote diffusion region which comprises the steps of: forming aninsulation layer over said surface; depositing a polysilicon layer oversaid insulation layer; selectively removing said polysilicon layer andunderlying insulation layer to expose said substrate through a window;defining a peripheral width of said polysilicon layer adjacent saidwindow for implantation of a doping element therethrough; implantingsaid doping element into said substrate through said window andperipheral width to form a central zone of buried contact aligned withsaid window and a peripheral zone of buried contact substantiallyaligned with said peripheral width, wherein said peripheral zonereceives a lesser amount of doping element than said central zone; andforming a selectively patterned conductive layer over said polysiliconlayer to form parts of said transistor, and access to said buriedcontact..Iaddend..Iadd.10. The process of claim 9, wherein the step ofimplanting comprises implanting into said substrate a doping elementselected from a group consisting of arsenic and phosphorous..Iaddend.